1. Field of the Invention
The present invention relates in general to a test circuit for testing the operation of a semiconductor memory device such as a dynamic random access memory (DRAM) to check whether it is normal or abnormal, and more particularly to an automatic test circuit for a semiconductor memory device which is capable of automatically testing the operation of the semiconductor memory device in data write and read modes to check whether it is normal or abnormal.
2. Description of the Prior Art
Generally, in a test mode, a semiconductor memory device receives test addresses directly from the outside to perform data read and write operations. However, a system comprising such a semiconductor memory device must alternately supply a row address strobe signal and a column address strobe signal to the memory device for the data read and write operations thereof in the test mode. As a result, it is very inconvenient to design such a system.